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INTEGRATED CIRCUITS
74LV107 Dual JK flip-flop with reset; negative-edge trigger
Product specification Supersedes data of 1997 Feb 03 IC24 Data Handbook 1998 Apr 20
Philips Semiconductors
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74LV107
FEATURES
* Wide operating: 1.0 to 5.5 V * Optimized for low voltage applications: 1.0 to 3.6 V * Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V * Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, * Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, * Output capability: standard * ICC category: flip-flops
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25C; tr = tf 2.5 ns SYMBOL PARAMETER Propagation delay nCP to nQ nCP to nQ nR to nQ, nQ Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop Tamb = 25C Tamb = 25C
DESCRIPTION
The 74LV107 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT107. The 74LV107 is a dual negative-edge triggered JK-type flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
CONDITIONS
TYPICAL 15 15 15 77 3.5
UNIT
tPHL/tPLH fmax CI CPD
CL = 15 pF; VCC = 3.3 V
ns
MHz pF pF
VI = GND to VCC1
30
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in W) fo) where: PD = CPD x VCC2 x fi ) (CL x VCC2 fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES 14-Pin Plastic DIL 14-Pin Plastic SO 14-Pin Plastic SSOP Type II 14-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +125C -40C to +125C -40C to +125C -40C to +125C OUTSIDE NORTH AMERICA 74LV107 N 74LV107 D 74LV107 DB 74LV107 PW NORTH AMERICA 74LV107 N 74LV107 D 74LV107 DB 74LV107PW DH PKG. DWG. # SOT27-1 SOT108-1 SOT337-1 SOT402-1
PIN CONFIGURATION
1J 1Q 1Q 1K 2Q 2Q GND 1 2 3 4 5 6 7 14 VCC 13 1R 12 1CP 11 2K 10 2R 9 8 2CP 2J
PIN DESCRIPTION
PIN NUMBER 1, 8, 4, 11 2, 6 3, 5 7 12, 9 13, 10 14 SYMBOL 1J, 2J, 1K, 2K 1Q, 2Q 1Q, 2Q GND 1CP, 2CP 1R, 2R VCC FUNCTION Synchronous inputs; flip-flops 1 and 2 Complement flip-flop outputs True flip-flop outputs Ground (0 V) Clock input (HIGH-to-LOW, edge-triggered) Asynchronous reset inputs (active LOW) Positive supply voltage
SV00497
1998 Apr 20
2
853-1904 19255
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74LV107
LOGIC SYMBOL
1 8 1J 2J J
LOGIC SYMBOL (IEEE/IEC)
1 1J 12 C1 Q 1Q 2Q 3 5 4 1K 13 1R CP FF 1Q Q 2Q 6 2 8 2J 9 K R 1R 13 2R 10 11 2K 10 2R 6 C1 5 2 3
12 1CP 9 2CP
4 11
1K 2K
SV00498
SV00499
FUNCTIONAL DIAGRAM
1 1J J Q 12 1CP CP 4 1K K R 13 8 1R 2J J Q 9 2CP CP 11 2K K R 10 2R FF2 2Q Q 6 2Q 5 FF1 1Q Q 2 1Q 3
SV00500
LOGIC DIAGRAM
K C C C C Q J C R C C C C C Q
CP
SV00501
1998 Apr 20
3
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74LV107
FUNCTION TABLE
INPUTS OPERATING MODES Asynchronous reset Toggle Load "0" (reset) Load "1" (set) Hold "no change" nR L H H H H nCP X nJ X h l h l nK X h h l l nQ L q L H q OUTPUTS nQ H q H L q
NOTES: H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW CP transition. X = don't care = HIGH-to-LOW CP transition
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL VCC "IIK "IOK "IO "IGND, "ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current - standard outputs DC VCC or GND current for types with - standard outputs Storage temperature range Power dissipation per package - plastic DIL - plastic mini-pack (SO) - plastic shrink mini-pack (SSOP and TSSOP) for temperature range: -40 to +125C above +70C derate linearly with 12 mW/K above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI < -0.5 or VI > VCC + 0.5V VO < -0.5 or VO > VCC + 0.5V -0.5V < VO < VCC + 0.5V CONDITIONS RATING -0.5 to +7.0 20 50 25 UNIT V mA mA mA
50 -65 to +150 750 500 400
mA C mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VO Tamb PARAMETER DC supply voltage Input voltage Output voltage Operating ambient temperature range in free air See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V CONDITIONS See Note 1 MIN 1.0 0 0 -40 -40 - - - - - - - - TYP. 3.3 - - MAX 5.5 VCC VCC +85 +125 500 200 100 50 UNIT V V V C
tr, tf
Input rise and fall times except for Schmitt-trigger inputs
ns/V
NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
1998 Apr 20
4
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74LV107
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VCC = 1.2 V VIH HIGH level Input voltage VCC = 2.0 V VCC = 2.7 to 3.6 V VCC = 4.5 to 5.5 V VCC = 1.2 V VIL LOW level Input voltage VCC = 2.0 V VCC = 2.7 to 3.6 V VCC = 4.5 to 5.5 VCC = 1.2 V; VI = VIH or VIL; -IO = 100A VOH HIGH level output voltage all outputs out uts voltage; VCC = 2.0 V; VI = VIH or VIL; -IO = 100A VCC = 2.7 V; VI = VIH or VIL; -IO = 100A VCC = 3.0 V; VI = VIH or VIL; -IO = 100A VCC = 4.5 V; VI = VIH or VIL; -IO = 100A VOH HIGH level output voltage; g STANDARD outputs VCC = 3.0 V; VI = VIH or VIL; -IO = 6mA VCC = 4.5 V; VI = VIH or VIL; -IO = 12mA VCC = 1.2 V; VI = VIH or VIL; IO = 100A VOL LOW level output voltage out uts voltage; all outputs VCC = 2.0 V; VI = VIH or VIL; IO = 100A VCC = 2.7 V; VI = VIH or VIL; IO = 100A VCC = 3.0 V; VI = VIH or VIL; IO = 100A VCC = 4.5 V; VI = VIH or VIL; IO = 100A VOL LOW level output voltage; g STANDARD outputs Input leakage current Quiescent supply current; flip-flops Additional quiescent supply current per input VCC = 3.0 V; VI = VIH or VIL; IO = 6mA VCC = 4.5 V; VI = VIH or VIL; IO = 12mA VCC = 5.5 V; VI = VCC or GND VCC = 5.5V; VI = VCC or GND; IO = 0 VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V 1.8 2.5 2.8 4.3 2.40 3.60 1.2 2.0 2.7 3.0 4.5 2.82 4.20 0 0 0 0 0 0.25 0.35 0.2 0.2 0.2 0.2 0.40 0.55 1.0 20.0 500 0.2 0.2 0.2 0.2 0.50 V 0.65 1.0 80 850 A A A V 1.8 2.5 2.8 4.3 2.20 V 3.50 V 0.9 1.4 2.0 0.7II ICC ICC
NOTE: 1. All typical values are measured at Tamb = 25C.
AC CHARACTERISTICS
GND = 0V; tr = tf 2.5ns; CL = 50pF; RL = 1K SYMBOL PARAMETER WAVEFORM CONDITION VCC(V) 1.2 2.0 tPHL/tPLH Propagation delay nCP to nQ, nQ Figures 1, 2 2.7 3.0 to 3.6 4.5 to 5.5 MIN LIMITS -40 to +85 C TYP1 95 32 24 182 44 33 26 22 56 41 33 28 ns MAX -40 to +125 C MIN MAX UNIT
1998 Apr 20
5
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74LV107
AC CHARACTERISTICS (Continued)
GND = 0V; tr = tf 2.5ns; CL = 50pF; RL = 1K SYMBOL PARAMETER WAVEFORM CONDITION VCC(V) 1.2 2.0 tPHL/tPLH Propagation delay nR to nQ, nQ Figures 1, 2 2.7 3.0 to 3.6 4.5 to 5.5 2.0 tW Clock pulse width HIGH or LOW Figure 2 2.7 3.0 to 3.6 4.5 to 5.5 2.0 tW Reset pulse width LOW Figure 2 2.7 3.0 to 3.6 4.5 to 5.5 1.2 2.0 trem Removal time nR to nCP Figure 2 2.7 3.0 to 3.6 4.5 to 5.5 1.2 2.0 tsu Set up time Set-up nJ, nK to CP Figure 1 2.7 3.0 to 3.6 4.5 to 5.5 1.2 2.0 th Hold time nJ, nK to CP Figure 1 2.7 3.0 to 3.6 4.5 to 5.5 2.0 fmax Maximum clock pulse frequency Figure 1 2.7 3.0 to 3.6 4.5 to 5.5 NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25C 2. Typical values are measured at VCC = 3.3 V. 5 5 5 5 14 19 24 30 40 58 702 26 19 15 12 -10 -3 -2 -22 5 5 5 5 12 16 20 24 MHz ns 24 18 14 11 40 14 10 82 31 23 18 15 ns 34 25 20 15 34 25 20 15 35 12 9 72 29 21 17 14 ns 14 10 82 14 10 82 MIN -40 to +85 C TYP1 95 32 24 182 44 33 26 22 41 30 24 18 41 30 24 ns ns 56 41 33 28 ns MAX -40 to +125 C MIN MAX UNIT
1998 Apr 20
6
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74LV107
AC WAVEFORMS
VM = 1.5 V at VCC 2.7 V and 3.6 V; VM = 0.5 x VCC at VCC < 2.7 V and 4.5 V; VOL and VOH are the typical output voltage drop that occur with the output load.
TEST CIRCUIT
Vcc
Vl VI nJ, nK INPUT GND PULSE GENERATOR RT t su th t su 1/f max th D.U.T.
VO
VM
50pF CL
RL= 1k
VI nCP INPUT GND
Test Circuit for Outputs
VM tW t PHL t PLH
DEFINITIONS
RL = Load resistor CL = Load capacitance includes jig and probe capacitiance RT = Termination resistance should be equal to ZOUT of pulse generators.
VOH nQ OUTPUT VOL VOH nQ OUTPUT VOL t PLH
VM
TEST tPLH/tPHL
VCC < 2.7V 2.7-3.6V
VI VCC 2.7V VCC
VM
4.5 V
SV00902
t PHL
Figure 3. Load circuitry for switching times.
The shaded areas indicate when the input is permitted to change for predictable output performance.
SV00504
Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the J and K to nCP set-up and hold times and the maximum clock pulse frequency.
VI nCP INPUT GND tW VI nR INPUT GND VM VM t rem
VOH nQ OUTPUT VOL t PLH VOH nQ OUTPUT VOL
t PHL VM
SV00502
Figure 2. Reset (nR) input to output (nQ, nQ) propagation delays, the reset pulse width and the nR to nCP removal time.
1998 Apr 20
7
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74LV107
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
1998 Apr 20
8
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74LV107
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
1998 Apr 20
9
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74LV107
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
1998 Apr 20
10
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74LV107
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
1998 Apr 20
11
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74LV107
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04416
Philips Semiconductors
1998 Apr 20 12

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